(a) Field of the Invention
The present invention relates to a wiring board used for mounting an electronic component such as a semiconductor element. Particularly, it relates to a wiring board having a structure including a core substrate used as a base material and wiring layers laminated on the respective surfaces of the core substrate.
Since such a wiring board plays a role in mounting a semiconductor element (chip) or the like, it is also referred to as a “semiconductor package” or simply a “package” for convenience in the description below.
(b) Description of the Related Art
A semiconductor package of a ball grid array
(BGA), land grid array (LGA), pin grid array (PGA) or other types is manufactured generally as follows. First, a core layer (core substrate) is prepared as a base material of the package. A multilayer wiring structure is formed on at least one surface of the core layer, for example, by a build-up process. The build-up process involves sequentially repeating formation of an insulating layer, formation of via holes in the insulating layer, and formation of a conductor pattern (wiring layer) inclusive of the insides of the via holes. Eventually, the outermost surface is covered with a protection film. The protection film is opened at a desired position to expose a portion (pad) of the conductor pattern. Furthermore, in the case of the BGA or PGA, a ball or a pin is bonded to the exposed pad as an external connection terminal.
A chip component such as a semiconductor element is mounted on one surface of such a semiconductor package. The semiconductor package is mounted on a mounting board such as a motherboard via the external connection terminals provided on the other surface of the semiconductor package. Namely, the chip component is electrically connected to the mounting board through the semiconductor package. For this reason, as means for electrically conducting between the two surfaces of the core substrate, through-holes are formed in the core substrate serving as the base material of the package. Each of the through-holes is filled with a conductive material. Connecting pads are provided on both ends of the conductor filled in each of the through-holes (i.e., on the surface of the core substrate). The connecting pad facilitates the interlayer connection between the wiring layers on the respective surfaces of the core substrate.
In the conventional method, a base material (for example, a plate having copper-clad laminates on both surfaces in the case of a plastic package; a green sheet obtained by binding a powder of alumina, aluminum nitride, or the like with an organic resin in the case of a ceramic package) having predetermined size and thickness is prepared in accordance with the type of the package, the function of the chip component to be mounted, and so forth. Through-holes (each having a diameter of approximately 300 μm in the state of the art) are formed at desired positions of the base material by a perforating process such as mechanical drilling. The resultant surface of the base material in the case of the ceramic package is further subjected to a metallizing process. Then, the resultant surface is subjected to, for example, electroplating in the case of the plastic package, or subjected to, for example, a screen printing method using a conductive paste in the case of the ceramic package. Thus, a conductor pattern (including the connecting pads) is formed in such a manner that the through-holes are filled with the conductive material.
Namely, for each desired package, a specific core substrate has to be prepared, which is then is subjected to a perforating process (formation of through-holes), metallizing process (formation of a metal layer), filling process (filling the through-holes with a conductor), and so forth.
An example of a technique related to the above-mentioned prior art is described in Japanese unexamined Patent Publication (JPP) (Kokai) 10-308565. A wiring board disclosed in this document has a structure including a core substrate in which filled-vias each having a uniform diameter of 300 μm or less are formed in a matrix pattern at equal pitches of 2 mm or less. A planar wiring pattern is formed on a surface of the core substrate with an insulating layer interposed therebetween. Each pad portion of the wiring pattern is electrically connected to the corresponding filled-via on a one-to-one basis through a communication-via which pierces the insulating layer.
As another related technique, JPP 2004-273480 describes a wiring board using, as a base material, a substrate made of a porous metal oxide film having multiple through-holes formed therein. Among the through-holes formed in the board, through-holes formed at positions where an electrode is disposed on the board are filled with a conductive material, while the other through-holes are filled with an insulating material.
To manufacture the conventional wiring board (package) as mentioned above, the following processes have to be performed. Specifically, through-holes are formed in a core substrate as means for electrically connecting between wiring layers on both sides of the core substrate. Further, connecting pads are formed on both surfaces of each through-hole (filled with a conductor). In forming the through-holes (including the connecting pads), a specific core substrate is prepared in accordance with the type of the package, the function of the chip component to be mounted, and so forth. The core substrate is subjected to, for example, perforating, metallizing, filling, and other processes.
Such a manufacturing procedure has the following problems. Specifically, it takes a long time to manufacture a core substrate suitable for the package, and an intended core substrate cannot be efficiently manufactured. Moreover, since the time to manufacture the core substrate is long, the overall manufacturing cost is increased.
Meanwhile, the diameter of each of the connecting pads has to be increased in accordance with the processing accuracy and alignment accuracy of the through-holes in the core substrate, the lamination accuracy of the wiring layers, and so forth. This leads to other problems of impaired freedom in wiring design and restriction in wiring density. Particularly, as smaller electronic devices or devices with other features are demanded, the diameter and arrangement pitch of the through-holes approach the achievable limits in the state of the art. Accordingly, the wiring density of the entire wiring board is further restricted.